1. Field of the Invention
This invention relates to non-synchronous clocked digital delay generator systems and, more particularly, to generating virtually jitter free delays relative to a start pulse and for generating such delays over both integer and non-integer multiples of the time interval between clocked timing pulses.
2. Description of the Prior Art
A typical prior art digital delay generator system generates a delay relative to a start pulse which is unsynchronized to timing pulses counted by the system. Because the start pulse is unsynchronized to the timing pulses, a period of time up to the time interval between timing pulses can occur between receipt of the start pulse and detection by the delay generator system of the first subsequent timing pulse. This uncertainty in time between the occurrence of the start pulse and the first counted timing pulse is commonly referred to as jitter. Accordingly, because the start pulse can occur at any time between adjacent timing pulses, and because the counter will only count at a specific point in the cycle between timing pulses, typically at the leading edge of each timing pulse, a jitter of up to the time interval between adjacent timing pulses will exist in the time delay established by the system.
Another disadvantage of typical digital delay generator systems is that, without supplementary circuitry, the nominal delays available are limited to integer multiples of the time interval between timing pulses. Therefore, nominal delays ending between timing pulses cannot be selected.